View AT89C2051X2_5273358.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? compatible with mcs-51 ? products 2k bytes of reprogrammable flash memory ? endurance: 1,000 write/erase cycles 2.7v to 6v operating range fully static operation: 0 hz to 12 mhz two-level program memory lock 128 x 8-bit internal ram 15 programmable i/o lines two 16-bit timer/counters six interrupt sources programmable serial uart channel direct led drive outputs on-chip analog comparator low-power idle and power-down modes 6clockspermachinecycleoperation description the AT89C2051X2 is a low-voltage, high-performance cmos 8-bit microcomputer with 2k bytes of flash programmable memory. the device is manufactured using atmel?s high-density nonvolatile memory technology and is compatible with the indus- try-standard mcs-51 instruction set. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel AT89C2051X2 is a powerful microcomputer which pro- vides a highly-flexible and cost-effective solution to many embedded control applications. the AT89C2051X2 provides the following standard features: 2k bytes of flash, 128 bytes of ram, 15 i/o lines, two 16-bit timer/counters, a five-vector, two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. in addition, the AT89C2051X2 is designed with static logic for oper- ation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset. furthermore, the AT89C2051X2 executes one machine cycle in 6 clock cycles, provid- ing twice the speed of the at89c2051 device. the user gains the flexibility to divide input frequency crystals by 2 (less expensive components), while keeping the same cpu power. alternatively, the user can save on power consumption while keeping the same cpu power (oscillator power saving). pin configuration pdip/soic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 rst/vpp (rxd) p3.0 (txd) p3.1 xtal2 xtal1 (int0) p3.2 (int1) p3.3 (to) p3.4 (t1) p3.5 gnd vcc p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 (ain1) p1.0 (ain0) p3.7 rev. 3285a?micro?12/02 8-bit microcontroller with 2k bytes flash AT89C2051X2 preliminary
2 AT89C2051X2 3285a?micro?12/02 block diagram
3 AT89C2051X2 3285a?micro?12/02 pin description vcc supply voltage. gnd ground. port 1 port 1 is an 8-bit bi-directional i/o port. port pins p1.2 to p1.7 provide internal pull-ups. p1.0 and p1.1 require external pull-ups. p1.0 and p1.1 also serve as the positive input (ain0) and the negative input (ain1), respectively, of the on-chip precision analog com- parator. the port 1 output buffers can sink 20 ma and can drive led displays directly. when 1s are written to port 1 pins, they can be used as inputs. when pins p1.2 to p1.7 are used as inputs and are externally pulled low, they will source current (i il ) because of the internal pull-ups. port 1 also receives code data during flash programming and verification. port 3 port 3 pins p3.0 to p3.5, p3.7 are seven bi-directional i/o pins with internal pull-ups. p3.6 is hard-wired as an input to the output of the on-chip comparator and is not acces- sible as a general purpose i/o pin. the port 3 output buffers can sink 20 ma. when 1s are written to port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pull-ups. port 3 also serves the functions of various special features of the AT89C2051X2 as listed below: port 3 also receives some control signals for flash programming and verification. rst reset input. all i/o pins are reset to 1s as soon as rst goes high. holding the rst pin high for two machine cycles while the oscillator is running resets the device. each machine cycle takes 6 oscillator or clock cycles. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. port pin alternate functions p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input)
4 AT89C2051X2 3285a?micro?12/02 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. figure 1. oscillator connections note: c1, c2 = 30 pf 10 pf for crystals =40pf 10 pf for ceramic resonators figure 2. external clock drive configuration
5 AT89C2051X2 3285a?micro?12/02 x2 mode description the clock for the entire circuit and peripherals is first divided by 2 before being used by the cpu core and peripherals. this allows any cyclic ratio (duty cycle) to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio (duty cycle) between 40% to 60%. figure 3 shows the clock generation block diagram. figure 3. clock generation block diagram 2 (xtal1)/2 f osc state machine: 6 clock cycles cpu control f xtal xtal1
6 AT89C2051X2 3285a?micro?12/02 special function registers a map of the on-chip memory area called the special function register (sfr) space is shown in the table below. note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return ran- dom data, and write accesses will have an indeterminate effect. user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. in that case, the reset or inactive values of the new bits will always be 0. table 1 . AT89C2051X2 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 0d7h 0c8h 0cfh 0c0h 0c7h 0b8h ip xxx00000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0xx00000 0afh 0a0h 0a7h 98h scon 00000000 sbuf xxxxxxxx 9fh 90h p1 11111111 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8fh 80h sp 00000111 dpl 00000000 dph 00000000 pcon 0xxx0000 87h
7 AT89C2051X2 3285a?micro?12/02 restrictions on certain instructions the AT89C2051X2 and is an economical and cost-effective member of atmel?s growing family of microcontrollers. it contains 2k bytes of flash program memory. it is fully com- patible with the mcs-51 architecture, and can be programmed using the mcs-51 instruction set. however, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. all the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2k for the AT89C2051X2. this should be the responsibility of the software program- mer. for example, ljmp 7e0h would be a valid instruction for the AT89C2051X2 (with 2k of memory), whereas ljmp 900h would not. branching instructions lcall, ljmp, acall, ajmp, sjmp, jmp @a+dptr these unconditional branching instructions will execute correctly as long as the pro- grammer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00h to 7ffh for the 89c2051x2). violating the physical space limits may cause unknown program behavior. cjne [...], djnz [...], jb, jnb, jc, jnc, jbc, jz, jnz with these conditional branching instructions the same rule above applies. again, violating the memory boundaries may cause erratic execution. for applications involving interrupts the normal interrupt service routine address loca- tions of the 80c51 family architecture have been preserved. movx-related instructions, data memory the AT89C2051X2 contains 128 bytes of internal data memory. thus, in the AT89C2051X2 the stack depth is limited to 128 bytes, the amount of available ram. external data memory access is not supported in this device, nor is external pro- gram memory execution. therefore, no movx [...] instructions should be included in the program. a typical 80c51 assembler will still assemble instructions, even if they are written in vio- lation of the restrictions mentioned above. it is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. program memory lock bits on the chip are two lock bits which can be left unprogrammed (u) or can be pro- grammed (p) to obtain the additional features listed in the table below: lock bit protection modes (1) note: 1. the lock bits can only be erased with the chip erase operation. program lock bits lb1 lb2 protection type 1 u u no program lock features. 2 p u further programming of the flash is disabled. 3 p p same as mode 2, also verify is disabled.
8 AT89C2051X2 3285a?micro?12/02 idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be termi- nated by any enabled interrupt or by a hardware reset. p1.0 and p1.1 should be set to ?0? if no external pull-ups are used, or set to ?1? if external pull-ups are used. it should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power-down mode in the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. the on-chip ram and special function registers retain their values until the power down mode is terminated. the only exit from power down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. p1.0 and p1.1 should be set to ?0? if no external pull-ups are used, or set to ?1? if external pull-ups are used. programming the flash the AT89C2051X2 is shipped with the 2k bytes of on-chip flash code memory array in the erased state (i.e., contents = ffh) and ready to be programmed. the code memory array is programmed one byte at a time. once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically. internal address counter: the AT89C2051X2 contains an internal memory address counter which is always reset to 000h on the rising edge of rst and is advanced by applying a positive going pulse to pin xtal1. programming algorithm: to program the AT89C2051X2, the following sequence is recommended. 1. power-up sequence: apply power between v cc and gnd pins set rst and xtal1 to gnd 2. set pin rst to ?h? set pin p3.2 to ?h? 3. apply the appropriate combination of ?h? or ?l? logic levels to pins p3.3, p3.4, p3.5, p3.7 to select one of the programming operations shown in the flash programming modes table. to program and verify the array: 4. apply data for code byte at location 000h to p1.0 to p1.7. 5. raise rst to 12v to enable programming. 6. pulse p3.2 once to program a byte in the program memory array or the lock bits. the byte-write cycle is self-timed and typically takes 1.2 ms.
9 AT89C2051X2 3285a?micro?12/02 7. to verify the programmed data, lower rst from 12v to logic ?h? level and set pins p3.3 to p3.7 to the appropriate levels. output data can be read at the port p1 pins. 8. to program a byte at the next address location, pulse xtal1 pin once to advance the internal address counter. apply new data to the port p1 pins. 9. repeat steps 6 through 8, changing data and advancing the address counter for the entire 2-kbyte array or until the end of the object file is reached. 10. power-off sequence: set xtal1 to ?l? set rst to ?l? tu r n v cc power off data polling: the AT89C2051X2 features data polling to indicate the end of a write cycle. during a write cycle, an attempted read of the last byte written will result in the complement of the written data on p1.7. once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated. ready/busy : theprogressofbyteprogrammingcanalsobemonitoredbythe rdy/bsy output signal. pin p3.1 is pulled low after p3.2 goes high during programming to indicate busy. p3.1 is pulled high again when programming is done to indicate ready. program verify: if lock bits lb1 and lb2 have not been programmed code data can be read back via the data lines for verification: 1. reset the internal address counter to 000h by bringing rst from ?l? to ?h?. 2. apply the appropriate control signals for read code data and read the output data at the port p1 pins. 3. pulse pin xtal1 once to advance the internal address counter. 4. read the next code data byte at the port p1 pins. 5. repeat steps 3 and 4 until the entire array is read. the lock bits cannot be verified directly. verification of the lock bits is achieved by observing that their features are enabled. chip erase: the entire program memory array (2k bytes) and the two lock bits are erased electrically by using the proper combination of control signals and by holding p3.2 low for 10 ms. the code array is written with all ?1?s in the chip erase operation and must be executed before any non-blank memory byte can be re-programmed. reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 000h, 001h, and 002h, except that p3.5 and p3.7 must be pulled to a logic low. the values returned are as follows. (000h) = 1eh indicates manufactured by atmel (001h) = 22h indicates 89c2051x2 programming interface everycodebyteintheflasharraycanbewrittenandtheentirearraycanbeerasedby using the appropriate combination of control signals. the write operation cycle is self- timed and once initiated, will automatically time itself to completion. most worldwide major programming vendors offer support for the atmel microcontroller series. please contact your local programming vendor for the appropriate software revision.
10 AT89C2051X2 3285a?micro?12/02 notes: 1. the internal memory address counter is reset to 000h on the rising edge of rst and is advanced by a positive pulse at xtal1 pin. 2. chip erase requires a 10 ms prog pulse. 3. p3.1 is pulled low during programming to indicate rdy/bsy . flash programming modes mode rst/vpp p3.2/prog p3.3 p3.4 p3.5 p3.7 write code data (1)(3) 12v l h h h read code data (1) hhllhh writelock bit-112v hhhh bit - 2 12v h h l l chip erase 12v h l l l read signature byte h h l l l l (2)
11 AT89C2051X2 3285a?micro?12/02 figure 4. programming the flash memory figure 5. verifying the flash memory 4.5v - 5.5v pgm data v ih /v pp rst gnd xtal1 p3.7 p3.5 p3.4 p3.3 p3.2 p1 v cc AT89C2051X2 see flash programming modes table rdy/bsy prog to increment address counter 4.5v - 5.5v pgm data v ih rst gnd xtal1 p3.7 p3.5 p3.4 p3.3 p3.2 p1 v cc AT89C2051X2 see flash programming modes table v ih
12 AT89C2051X2 3285a?micro?12/02 note: 1. only used in 12-volt programming mode. flash programming and verification waveforms flash programming and verification characteristics t a = 0c to 70c, v cc = 5.0 10% symbol parameter min max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvgl data setup to prog low 1.0 s t ghdx data hold after prog 1.0 s t ehsh p3.4 (enable )hightov pp 1.0 s t shgl v pp setup to prog low 10 s t ghsl v pp hold after prog 10 s t glgh prog width 1 110 s t elqv enable low to data valid 1.0 s t ehqz data float after enable 01.0 s t ghbl prog high to busy low 50 ns t wc byte write cycle time 2.0 ms t bhih rdy/bsy \ to increment clock delay 1.0 s t ihil increment clock high 200 ns
AT89C2051X2 13 notes: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol perportpin:20ma maximum total i ol for all output pins: 80 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum v cc for power-down is 2v. absolute maximum ratings* operating temperature ................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage ............................................ 6.6v dc output current...................................................... 25.0 ma dc characteristics t a = -40c to 85c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min max units v il input low-voltage -0.5 0.2 v cc -0.1 v v ih input high-voltage (except xtal1, rst) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high-voltage (xtal1, rst) 0.7 v cc v cc +0.5 v v ol output low-voltage (1) (ports 1, 3) i ol =20ma,v cc =5v i ol =10ma,v cc =2.7v 0.5 v v oh output high-voltage (ports 1, 3) i oh = -80 a, v cc =5v 10% 2.4 v i oh = -30 a 0.75 v cc v i oh = -12 a 0.9 v cc v i il logical 0 input current (ports 1, 3) v in = 0.45v -50 a i tl logical 1 to 0 transition current (ports 1, 3) v in =2v,v cc =5v 10% -750 a i li input leakage current (port p1.0, p1.1) 0 14 AT89C2051X2 3285a?micro?12/02 external clock drive waveforms external clock drive symbol parameter v cc =2.7vto6.0v v cc = 4.0v to 6.0v units min max min max 1/t clcl oscillator frequency 0 6 0 12 mhz t clcl clock period 166.6 83.3 ns t chcx high time 60 30 ns t clcx low time 60 30 ns t clch rise time 5 5 ns t chcl fall time 5 5 ns t chcx /t clcx cyclic ratio (duty cycle) 40 60 40 60 %
15 AT89C2051X2 3285a?micro?12/02 () shift register mode timing waveforms ac testing input/output waveforms (1) note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at v ih min. for a logic 1 and v il max. for a logic 0. serial port timing: shift register mode test conditions v cc =5.0v 20%; load capacitance = 80 pf symbol parameter 12 mhz osc variable oscillator units min max min max t xlxl serial port clock cycle time 1.0 12t clcl s t qvxh output data setup to clock rising edge 700 10t clcl -133 ns t xhqx output data hold after clock rising edge 50 2t clcl -117 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10t clcl -133 ns
16 AT89C2051X2 3285a?micro?12/02 float waveforms (1) note: 1. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when 100 mv change from the loaded v oh /v ol level occurs.
17 AT89C2051X2 3285a?micro?12/02 notes: 1. xtal1tiedtogndfori cc (power-down). 2. p.1.0 and p1.1 = v cc or gnd. 3. lock bits programmed. AT89C2051X2 typical icc - active (85?c) 0 5 10 15 20 036912 frequency (mhz) i c c m a vcc=6.0v vcc=5.0v vcc=3.0v AT89C2051X2 typical icc - idle (85 ? c) 0 1 2 3 0 1.5 3 4.5 6 frequency (mhz) i c c m a vcc=6.0v vcc=5.0v vcc=3.0v AT89C2051X2 typical icc vs. voltage - power down (85 ? c) 0 5 10 15 20 3.0v 4.0v 5.0v 6.0v vcc voltage i c c a
18 AT89C2051X2 3285a?micro?12/02 ordering information speed (mhz) power supply ordering code package operation range 6 2.7v to 6.0v AT89C2051X2-6pc AT89C2051X2-6sc 20p3 20s2 commercial (0 cto70 c) AT89C2051X2-6pi AT89C2051X2-6si 20p3 20s2 industrial (-40 cto85 c) 12 4.0v to 6.0v AT89C2051X2-12pc AT89C2051X2-12sc 20p3 20s2 commercial (0 cto70 c) AT89C2051X2-12pi AT89C2051X2-12si 20p3 20s2 industrial (-40 cto85 c) package type 20p3 20-lead, 0.300? wide, plastic dual in-line package (pdip) 20s2 20-lead, 0.300? wide, plastic gull wing small outline (soic)
19 AT89C2051X2 3285a?micro?12/02 package information 20p3 pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 20p3 09/28/01 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 25.984 ? 25.493 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
20 AT89C2051X2 3285a?micro?12/02 20s2 soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s2 , 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 1/9/02 20s2 a l a1 end view side view top view h e b n 1 e a d c common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation ac for additional information. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exc eed 0.15 mm (0.006") per side. 3. dimension "e" does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "l" is the length of the terminal for soldering to a substrate. 5. the lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. a 0.0926 0.1043 a1 0.0040 0.0118 b 0.0130 0.0200 4 c 0.0091 0.0125 d 0.4961 0.5118 1 e 0.2914 0.2992 2 h 0.3940 0.4190 l 0.0160 0.050 3 e 0.050 bsc
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 3285a?micro?12/02 xm at m e l ? is a registered trademark of atmel. terms and product names in this document may be trademarks of others.

▲Up To Search▲

Price & Availability of AT89C2051X2

	To Download AT89C2051X2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .